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DS1553 64k nv y2kc timekeeping ram DS1553 preliminary 070198 1/19 features ? integrated nv sram, real time clock, crystal, power fail control circuit and lithium energy source ? clock registers are accessed identical to the static ram. these registers are resident in the sixteen top ram locations ? totally nonvolatile with over 10 years of operation in the absence of power ? precision poweron reset ? programmable watchdog timer and rtc alarm ? bcd coded century, year, month, date, day, hours, minutes, and seconds with automatic leap year com- pensation valid up to the year 2100 ? battery voltage level indicator flag ? powerfail write protection allows for 10% vcc power supply tolerance ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ordering information DS1553pxxx 70 70 ns access (5 volt) 100 ns access 100 *DS1553wpxxx 120 120 ns access 150 ns access 150 (3.3 volt) *ds9034pcx (powercap) required: must be ordered seperately blank 28pin dip module p 34pin powercap module board* blank 28pin dip module p 34pin powercap module board* pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 34pin powercap module board (uses ds9034pcx powercap 14 15 16 17 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 vcc we irq /ft a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 rst a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28pin encapsulated package (700 mil extended x1 gnd v bat x2 irq /ft nc nc rst v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd nc nc nc nc a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 pin description a0a12 address input dq0dq7 data input/outputs irq \ft interrupt, frequency test output (open drain) rst poweron reset output (open drain) ce chip enable oe output enable we write enable v cc power supply input gnd ground nc no connection
DS1553 070198 2/19 description the DS1553 is a full function, year 2000 compliant (y2kc), realtime clock/calendar (rtc) with a rtc alarm, watchdog timer, poweron reset, battery monitor, and 8k x 8 nonvolatile static ram. user access to all registers within the DS1553 is accomplished with a bytewide interface as shown in figure 1. the rtc regis- ters contain century, year, month, date, day, hours, min- utes, and seconds data in 24 hour bcd format. correc- tions for day of month and leap year are made automatically. the rtc registers are double buffered into an internal and external set. the user has direct access to the external set. clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. assuming the internal oscil- lator is turned on, the internal set of registers are contin- uously updated; this occurs regardless of external reg- isters settings to guarantee that accurate rtc information is always maintained. the DS1553 has interrupt (irq /ft) and reset (rst ) outputs which can be used to control cpu activity. the irq /ft interrupt output can be used to generate an external interrupt when the rtc register values match user programmed alarm values. the interrupt is always available while the device is powered from the system supply and can be programmed to occur when in the battery backed state to serve as a system wakeup. either the irq /ft or rst outputs can also be used as a cpu watchdog timer, cpu activity is monitored and an interrupt or reset output will be activated if the correct activity is not detected within programmed limits. the DS1553 poweron reset can be used to detect a system power down or failure and hold the cpu in a safe reset state until normal power returns and stabilizes; the rst output is used for this function. the DS1553 also contains its own power fail circuitry which automatically deselects the device when the v cc supply enters an out of tolerance condition. this feature provides a high degree of data security during unpre- dictable system operation brought on by low v cc levels. packages the DS1553 is available in two packages (28pin dip and 34pin powercap module). the 28pin dip style module integrates the crystal, lithium energy source, and silicon all in one package. the 34pin powercap module board is designed with contacts for connection to a separate powercap (ds9034pcx) that contains the crystal and battery. this design allows the power- cap to be mounted on top of the DS1553p after the completion of the surface mount process. mounting the powercap after the surface mount process prevents damage to the crystal and battery due to the high tem- peratures required for solder reflow. the powercap is keyed to prevent reverse insertion. the powercap module board and powercap are ordered separately and shipped in separate containers. the part number for the powercap is ds9034pcx. DS1553 block diagram figure 1 clock alarm, and power control 16 x 8 clock and control 8176 x 8 ce we oe v cc rst irq /ft a0a12 dq0dq7 nv sram registers watchdog countdown write protection, and poweron reset 32.768 khz clock osc v bat
DS1553 070198 3/19 DS1553 operating modes table 1 v cc ce oe we dq0dq7 a0a12 mode power itl v ih x x highz x deselect standby in tolerance v il x v il d in a in write active i n t o l erance v il v il v ih d out a in read active v il v ih v ih highz a in read active v bat < v cc < tolerance x x x highz x deselect cmos standby DS1553 is in the read mode whenever ce (chip enable) is low and we (write enable) is high. the device architecture allows ripple through access to any valid address location. valid data will be available at the dq pins within t aa after the last address input is stable, pro- viding that ce and oe access times are satisfied. if ce or oe access times are not met, valid data will be avail- able at the latter of chip enable access (t cea ) or at out- put enable access time (t oea ). the state of the data input/output pins (dq) is controlled by ce and oe . if the outputs are activated before t aa , the data lines are driven to an intermediate state until t aa . if the address inputs are changed while ce and oe remain valid, out- put data will remain valid for output data hold time (t oh ) but will then go indeterminate until the next address access. data write mode the DS1553 is in the write mode whenever we and ce are in their active state. the start of a write is referenced to the latter occurring transition of we or ce . the addresses must be held valid throughout the cycle. ce and we must return inactive for a minimum of t wr prior to the initiation of a subsequent read or write cycle. data in must be valid t ds prior to the end of the write and remain valid for t dh afterward. in a typical application, the oe signal will be high during a write cycle. however, oe can be active provided that care is taken with the data bus to avoid bus contention. if oe is low prior to we transitioning low, the data bus can become active with read data defined by the address inputs. a low tran- sition on we will then disable the outputs t wez after we goes active. data retention mode the 5 volt device is fully accessible and data can be writ- ten and read only when v cc is greater than v pf . how- ever, when v cc is below the power fail point v pf (point at which write protection occurs) the internal clock regis- ters and sram are blocked from any access. when v cc falls below the battery switch point v so (battery supply level), device power is switched from the v cc pin to the internal backup lithium battery. rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. the 3.3 volt device is fully accessible and data can be written and read only when v cc is greater than v pf . when v cc falls below v pf , access to the device is inhib- ited. if v pf is less than v bat , the device power is switched from v cc to the internal backup lithium battery when v cc drops below v pf . if v pf is greater than v bat , the device power is switched from v cc to the internal backup lithium battery when v cc drops below v bat . rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. all control, data, and address signals must be powered down when v cc is powered down. battery longevity the DS1553 has a lithium power source that is designed to provide energy for the clock activity, and clock and ram data retention when the v cc supply is not present. the capability of this internal power supply is sufficient to power the DS1553 continuously for the life of the equipment in which it is installed. for specifi- cation purposes, the life expectancy is 10 years at 25 c
DS1553 070198 4/19 with the internal clock oscillator running in the absence of v cc . each DS1553 is shipped from dallas semicon- ductor with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v pf , the lithium energy source is enabled for battery backup operation. actual life expectancy of the DS1553 will be much longer than 10 years since no internal battery energy is consumed when v cc is present. in fact, in most applications, the life expectancy of the DS1553 will be approximately equal to the shelf life (expected useful life of the internal lithium battery with no load attached) of the battery which may prove to be as long as 20 years. internal battery monitor the DS15533 constantly monitors the battery voltage of the internal batter. the battery low flag (blf) bit of the flags register (b4 of 1ff0h) is not writable and should always be a a0o when read. if a a1o is ever present, an exhausted lithium energy source is indicated and both the contents of the rtc and ram are questionable. poweron reset a temperature compensated comparator circuit moni- tors the level of v cc . when v cc falls to the power fail trip point, the rst signal (open drain) is pulled low. when v cc returns to nominal levels, the rst signal continues to be pulled low for a period of 40 ms to 200 ms. the poweron reset function is independent of the rtc oscillator and thus is operational whether or not the oscillator is enabled. clock operations table 2 and the following paragraphs describe the operation of rtc, alarm, and watchdog functions. DS1553 register map table 2 address data function/range address b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 function/range 1fffh 10 year year year 0099 1ffeh x x x 10 m month month 0112 1ffdh x x 10 date date date 0131 1ffch x ft x x x day day 0107 1ffbh x x 10 hour hour hour 0023 1ffah x 10 minutes minutes minutes 0059 1ff9h osc 10 seconds seconds seconds 0059 1ff8h w r 10 century century control 0039 1ff7h wds bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 1ff6h ae y abe y y y y y interrupts 1ff5h am4 y 10 date date alarm date 0131 1ff4h am3 y 10 hours hours alarm hours 0023 1ff3h am2 10 minutes minutes alarm minutes 0059 1ff2h am1 10 seconds seconds alarm seconds 0059 1ff1h y y y y y y y y unused 1ff0h wf af 0 blf 0 0 0 0 flags x = unused, read/writable under write and read ae = alarm flag enable bit control y = unused, read/writable without write and read ft = frequency test bit bit control osc = oscillator start/stop bit abe = alarm in battery backup mode enable w = write bit am1am4 = alarm mask bits r = read bit wf = watchdog flag
DS1553 070198 5/19 wds = watchdog steering bit af = alarm flag bmb0bmb4 = watchdog multiplier bits 0 = a0o and are read only rb0rb1 = watchdog resolution bits blf = battery low flag clock oscillator control the clock oscillator may be stopped at any time. to increase the shelf life of the backup lithium battery source, the oscillator can be turned off to minimize cur- rent drain from the battery. the osc bit is the msb of the seconds register (b7 of 1ff9h). setting it to a a1o stops the oscillator, setting to a a0o starts the oscillator. the DS1553 is shipped from dallas semiconductor with the clock oscillator turned off, osc bit set to a a1o. reading the clock when reading the rtc data, it is recommended to halt updates to the external set of double buffered rtc reg- isters. this puts the external registers into a static state allowing data to be read without register values chang- ing during the read process. normal updates to the internal registers continue while in this state. external updates are halted when a a1o is written into the read bit, b6 of the control register (1ff8h). as long as a a1o remains in the control register read bit, updating is halted. after a halt is issued, the registers reflect the rtc count (day, date, and time) that was current at the moment the halt command was issued. normal updates to the external set of registers will resume within 1 second after the read bit is set to a a0o. setting the clock the eighth bit, b7 of the control register is the write bit. setting the write bit to a a1o, like the read bit, halts updates to the DS1553 (1ff8h1fffh) registers. after setting the write bit to a a1o, rtc registers can be loaded with the desired rtc count (day, date, and time) in 24 hour bcd format. setting the write bit to a a0o then trans- fers the values written to the internal rtc registers and allows normal operation to resume. clock accuracy (dip module) the DS1553 is guaranteed to keep time accuracy to within 1 minute per month at 25 c. the rtc is cali- brated at the factory by dallas semiconductor using nonvolatile tuning elements. the DS1553 does not require additional calibration and, in most applications, temperature deviations will have a negligible effect on accuracy. for this reason, methods of field clock cal- ibration are not available and not necessary. attempts to calibrate the rtc that may be used with similar device types (m48t5x family) will not have any effect even though the DS1553 appears to accept calibration data. clock accuracy (powercap module) the DS1553 and ds9034pcx are each individually tested for accuracy. once mounted together, the mod- ule is guaranteed to keep time accuracy to within 1.53 minutes per month (35 ppm) at 25 c. frequency test mode the DS1553 frequency test mode uses the open drain irq /ft output. with the oscillator running, the irq /ft output will toggle at 512 hz when the ft bit is a a1o, the alarm flag enable bit (ae) is a a0o, and the watchdog steering bit (wds) is a a1o or the watchdog register is reset (register 1ff7h = 00h). the irq /ft output and the frequency test mode can be used as a measure of the actual frequency of the 32.768 khz rtc oscillator. the irq /ft pin is an open drain output which requires a pullup resistor for proper operation. the ft bit is cleared to a a0o on powerup. using the clock alarm the alarm settings and control for the DS1553 reside within registers 1ff2h 1ff5h. register 1ff6h con- tains two alarm enable bits: alarm enable (ae) and alarm in backup enable (abe). the ae and abe bits must be set as described below for the irq /ft output to be activated for a matched alarm condition. the alarm can be programmed to activate on a specific day of the month or repeat every day, hour, minute, or second. it can also be programmed to go off while the DS1553 is in the battery backed state of operation to serve as a system wakeup. alarm mask bits am1am4 control the alarm mode. table 3 shows the possible settings. configurations not listed in the table default to the once per second mode to notify the user of an incorrect alarm setting.
DS1553 070198 6/19 alarm mask bits table 3 am4 am3 am2 am1 alarm rate 1 1 1 1 once per second 1 1 1 0 when seconds match 1 1 0 0 when minutes and seconds match 1 0 0 0 when hours, minutes, and seconds match 0 0 0 0 when date, hours, minutes, and seconds match when the rtc register values match alarm register set- tings, the alarm flag bit (af) is set to a a1o. if alarm flag enable (ae) is also set to a a1o, the alarm condition acti- vates the irq /ft pin. the irq /ft signal is cleared by a read or write to the flags register (address 1ff0h) as shown in figure 2 and 3. the irq /ft signal may be cleared by having the address stable for as short as 15 ns and either ce or we active, but is not guaranteed to be cleared unless t rc is fulfilled. the alarm flag is also cleared by a read or write to the flags register but the flag will not change states untilthe end of the read/write cycle and the irq/ft signal has been cleared. clearing irq waveforms figure 2 a0a12 irq /ft 15 ns min address 1ff0h highz we , oe , ov clearing irq waveforms figure 3 a0a12 irq /ft 15 ns min address 1ff0h highz we , oe
DS1553 070198 7/19 the irq /ft pin can also be activated in the battery backedup mode. the irq /ft will go low if an alarm occurs and both abe and ae are set. the abe and ae bits are cleared during the powerup transition, how- ever an alarm generated during powerup will set af. therefore the af bit can be read after system powerup to determine if an alarm was generated during the pow- erup sequence. figure 4 illustrates alarm timing dur- ing the battery backup mode and powerup states. backup mode alarm waveforms figure 4 v cc abe, ae af irq /ft v pf(max) v pf(min) highz highz using the watchdog timer the watchdog timer can be used to detect an outof control processor. the user programs the watchdog timer by setting the desired amount of timeout into the eight bit watchdog register (address 1ff7h). the five watchdog register bits bmb4bmb0 store a binary multiplier and the two lower order bits rb1rb0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. the watchdog time out value is then determined by the multiplication of the five bit multiplier value with the two bit resolution value. (for example: writing 00001110 in the watchdog regis- ter = 3 x 1 second or 3 seconds). if the processor does not reset the timer within the specified period, the watchdog flag (wf) is set and a processor interrupt is generated and stays active until either the watchdog flag (wf) is read or the watchdog register (1ff7) is read or written. the most significant bit of the watchdog register is the watchdog steering bit (wds). when set to a a0o, the watchdog will activate the irq /ft output when the watchdog times out. when wds is set to a a1o, the watchdog will output a negative pulse on the rst output for a duration of 40ms to 200 ms. the watchdog register (1ff7) and the ft bit will reset to a at the end of a watchdog timeout when the wds bit is set to a a1o. the watchdog timer resets when the processor per- forms a read or write of the watchdog register. the timeout period then starts over. the watchdog timer is disabled by writing a value of 00h to the watchdog regis- ter. the watchdog function is automatically disabled upon powerup and the watchdog register is cleared. if the watchdog function is set to output to the irq /ft out- put and the frequency test function is activated, the watchdog function prevails and the frequency test func- tion is denied. poweron default states upon application of power to the device, the following register bits are set to a a0o: wds=a0o, bmb0bmb4=a0o, rb0rb1=a0o, ae=a0o, abe=a0o.
DS1553 070198 8/19 absolute maximum ratings* voltage on any pin relative to ground 5.0v to +6.0v operating temperature 0 c to 70 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds (see note 8) * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes logic 1 voltage all inputs v cc = 5v 10% v ih 2.2 v cc +0.3v v 1 v cc = 3.3v 10% v ih 2.0 v cc +0.3v v 1 logic 0 voltage all inputs v cc = 5v 10% v il 0.3 0.8 1 v cc = 3.3v 10% v il 0.3 0.6 1 dc electrical characteristics (0 c to 70 c; v cc = 5.0v 10%) parameter symbol min typ max units notes active supply current i cc 15 50 ma 2, 3 ttl standby current (ce =v ih ) i cc1 1 3 ma 2, 3 cmos standby current (ce v cc 0.2v) i cc2 1 3 ma 2, 3 input leakage current (any input) i il 1 +1 m a output leakage current (any output) i ol 1 +1 m a output logic 1 voltage (i out = 1.0 ma) v oh 2.4 v 1 output logic 0 voltage (i out = 2.1 ma, dq07 outputs) v ol1 0.4 v 1 (i out = 10.0 ma, irq /ft and rst outputs) v ol2 0.4 v 1, 5 write protection voltage v pf 4.25 4.37 4.50 v 1 battery switch over voltage v so v bat v 1, 4
DS1553 070198 9/19 dc electrical characteristics (0 c to 70 c; v cc = 3.3v 10%) parameter symbol min typ max units notes active supply current i cc 10 30 ma 2, 3 ttl standby current (ce = v ih ) i cc1 0.7 2 ma 2, 3 cmos standby current (ce v cc 0.2v) i cc2 0.7 2 ma 2, 3 input leakage current (any input) i il 1 +1 m a output leakage current (any output) i ol 1 +1 m a output logic 1 voltage (i out = 1.0 ma) v oh 2.4 v 1 output logic 0 voltage (i out =2.1 ma, dq07 outputs) v ol1 0.4 v 1 (i out =10.0 ma, irq /ft and rst outputs) v ol2 0.4 v 1, 5 write protection voltage v pf 2.80 2.88 2.97 v 1 battery switch over voltage v so v bat or v pf v 1, 4 read cycle timing diagram figure 5 a0a12 ce oe dq0dq7 t rc t aa t cea t cel t oea t oel valid t oh t cez t oez
DS1553 070198 10/19 read cycle, ac characteristics (0 c to 70 c; v cc = 5.0v 10%) parameter symbol 70 ns access 100 ns access units notes parameter symbol min max min max units notes read cycle time t rc 70 100 ns address access time t aa 70 100 ns ce to dq lowz t cel 5 5 ns ce access time t cea 70 100 ns ce data off time t cez 25 35 ns oe to dq lowz t oel 5 5 ns oe access time t oea 35 55 ns oe data off time t oez 25 35 ns output hold from address t oh 5 5 ns read cycle, ac characteristics (0 c to 70 c; v cc = 3.3v 10%) parameter symbol 120 ns access 150 ns access units notes parameter symbol min max min max units notes read cycle time t rc 120 150 ns address access time t aa 120 150 ns ce dq lowz t cel 5 5 ns ce access time t cea 120 150 ns ce data off time t cez 40 50 ns oe dq lowz t oel 5 5 ns oe access time t oea 100 130 ns oe data off time t oez 35 35 ns output hold from address t oh 5 5 ns
DS1553 070198 11/19 write cycle, ac characteristics (0 c to 70 c; v cc = 5.0v 10%) parameter symbol 70 ns access 100 ns access units notes parameter symbol min max min max units notes write cycle time t wc 70 100 ns address setup time t as 0 0 ns we pulse width t wew 50 70 ns ce pulse width t cew 55 75 ns data setup time t ds 30 40 ns data hold time t dh 0 0 ns address hold time t ah 0 0 ns we data off time t wez 25 35 ns write recovery time t wr 5 5 ns write cycle, ac characteristics (0 c to 70 c; v cc = 3.3v 10%) parameter symbol 120 ns access 150 ns access units notes parameter symbol min max min max units notes write cycle time t wc 120 150 ns address setup time t as 0 0 ns we pulse width t wew 100 130 ns ce pulse width t cew 110 140 ns data setup time t ds 80 90 ns data hold time t dh 0 0 ns address hold time t ah 0 0 ns we data off time t wez 40 50 ns write recovery time t wr 10 10 ns
DS1553 070198 12/19 write cycle timing, write enable controlled figure 6 a0a12 ce we dq0dq7 t wc t as t wew t wez valid t wr valid data output data input data input t as t ah t ds t dh write cycle timing, chip enable controlled figure 7 a0a12 ce we dq0dq7 t wc t as valid t wr valid data input data input t ah t ds t dh t as t cew
DS1553 070198 13/19 powerup/down characteristics (0 c to 70 c; v cc = 5.0v 10%) parameter symbol min typ max units notes ce or we at v ih , before powerdown t pd 0 m s v cc fall time: v pf(max) to v pf(min) t f 300 m s v cc fall time: v pf(min) to v so t fb 10 m s v cc rise time: v pf(min) to v pf(max) t r 0 m s v pf to rst high t rec 40 200 ms expected data retention time (oscillator on) t dr 10 years 6, 7 powerup/down waveform timing 5 volt device figure 8 v cc t fb inputs t f v pf(max) v pf(min) t r rst v so t pd t dr t rec outputs don't care highz recognized valid valid recognized
DS1553 070198 14/19 powerup/down characteristics (0 c to 70 c; v cc = 3.3v 10%) parameter symbol min typ max units notes ce or we at v ih , before powerdown t pd 0 m s v cc fall time: v pf(max) to v pf(min) t f 300 m s v cc rise time: v pf(min) to v pf(max) t r 0 m s v pf to rst high t rec 40 200 ms expected data retention time (oscillator on) t dr 10 years 6, 7 powerup/down waveform timing 3.3 volt device figure 9 v cc inputs t f v pf(max) v pf(min) t r rst t pd t rec outputs don't care highz recognized valid valid recognized capacitance (t a = 25 c) parameter symbol min typ max units notes capacitance on all input pins c in 7 pf 1 capacitance on irq /ft, rst , and dq pins c io 10 pf 1
DS1553 070198 15/19 ac test conditions output load: 100 pf + 1ttl gate input pulse levels: 0.0 to 3.0 volts timing measurement reference levels: input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns notes: 1. voltage referenced to ground. 2. typical values are at 25 c and nominal supplies. 3. outputs are open. 4. battery switch over occurs at the lower of either the battery voltage or v pf . 5. the irq /ft and rst outputs are open drain. 6. data retention time is at 25 c. 7. each DS1553 has a builtin switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined for dip modules as a cumulative time in the absence of v cc starting from the time power is first applied by the user. 8. realtime clock modules (dip) can be successfully processed through conventional wavesoldering tech- niques as long as temperature exposure to the lithium energy source contained within does not exceed +85 c. post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. in addition, for the powercap: a. dallas semiconductor recommends that powercap module bases experience one pass through solder reflow oriented with the label side up (alive bugo). b. hand soldering and touchup: do not touch or apply the soldering iron to leads for more than 3 (three) seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflow and use a solder wick to remove solder.
DS1553 070198 16/19 DS1553 28pin package a 1 dim min max a in. mm b in. mm c in. mm d in. mm e in. mm f in. mm g in. mm h in. mm j in. mm k in. mm 1.470 37.34 1.490 37.85 0.675 17.75 0.740 18.80 0.335 8.51 0.355 9.02 0.075 1.91 0.105 2.67 0.015 0.38 0.030 0.76 0.140 3.56 0.180 4.57 0.090 2.29 0.110 2.79 0.590 14.99 0.630 16.00 0.010 0.25 0.018 0.45 0.015 0.43 0.025 0.58 c f g k d h b e j 28pin pkg
DS1553 070198 17/19 DS1553p dim min nom a 0.920 0.925 b 0.980 0.985 c d 0.052 0.055 e 0.048 0.050 f 0.015 0.020 g 0.025 0.027 pkg inches max 0.930 0.990 0.080 0.058 0.052 0.025 0.030 top view side view bottom view
DS1553 070198 18/19 DS1553p with ds9034pcx attached dim min nom a 0.920 0.925 b 0.955 0.960 c 0.240 0.245 d 0.052 0.055 e 0.048 0.050 f 0.015 0.020 g 0.020 0.025 pkg inches max 0.930 0.965 0.250 0.058 0.052 0.025 0.030 top view side view bottom view
DS1553 070198 19/19 recommended powercap module land pattern pkg dim inches min nom max a 1.050 b 0.826 c 0.050 d 0.030 e 0.112 a d b c e 16 pl

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